## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn54x)
## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn54x)
###############################################################################
# Application options
# Logging Levels
# NXPLOG_DEFAULT_LOGLEVEL 0x01
# ANDROID_LOG_DEBUG 0x03
# ANDROID_LOG_WARN 0x02
# ANDROID_LOG_ERROR 0x01
# ANDROID_LOG_SILENT 0x00
#
NXPLOG_EXTNS_LOGLEVEL=0x01
NXPLOG_NCIHAL_LOGLEVEL=0x01
NXPLOG_NCIX_LOGLEVEL=0x01
NXPLOG_NCIR_LOGLEVEL=0x01
NXPLOG_FWDNLD_LOGLEVEL=0x01
NXPLOG_TML_LOGLEVEL=0x01
###############################################################################
# Nfc Device Node name
NXP_NFC_DEV_NODE="/dev/pn551"
###############################################################################
# Extension for Mifare reader enable
MIFARE_READER_ENABLE=0x01
###############################################################################
# Vzw Feature enable
VZW_FEATURE_ENABLE=0x01
###############################################################################
# File name for Firmware
NXP_FW_NAME="libpn551_fw.so"
###############################################################################
# System clock source selection configuration
#define CLK_SRC_XTAL 1
#define CLK_SRC_PLL 2
NXP_SYS_CLK_SRC_SEL=0x01
###############################################################################
# System clock frequency selection configuration
#define CLK_FREQ_13MHZ 1
#define CLK_FREQ_19_2MHZ 2
#define CLK_FREQ_24MHZ 3
#define CLK_FREQ_26MHZ 4
#define CLK_FREQ_38_4MHZ 5
#define CLK_FREQ_52MHZ 6
NXP_SYS_CLK_FREQ_SEL=0x01
###############################################################################
# The timeout value to be used for clock request acknowledgment
# min value = 0x01 to max = 0x06
NXP_SYS_CLOCK_TO_CFG=0x06
###############################################################################
# NXP proprietary settings
NXP_ACT_PROP_EXTN={2F, 02, 00}
###############################################################################
# NFC forum profile settings
NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00}
###############################################################################
# NFCC Configuration Control
# Allow NFCC to manage RF Config 0x01
# Don't allow NFCC to manage RF Config 0x00
NXP_NFC_MERGE_RF_PARAMS={20, 02, 04, 01, 85, 01, 01}
###############################################################################
# Standby enable settings
NXP_CORE_STANDBY={2F, 00, 01, 01}
###############################################################################
# NXP TVDD configurations settings
# Allow NFCC to configure External TVDD, There are currently three
#configurations (1, 2 and 3) are supported, out of them only one can be
#supported.
NXP_EXT_TVDD_CFG=0x02
#config1:SLALM, 3.3V for both RM and CM
NXP_EXT_TVDD_CFG_1={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 02, 09, 00}
#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
#monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, 40, 0A }
###############################################################################
# NXP RF ALMSL configuration settings for FW VERSION = 10.05.02
#
# A0, 0D, 03, 00, 40, 01 RF_CLIF_CFG_BOOT CLIF_ANA_NFCLD_REG
# A0, 0D, 03, 04, 47, 02 RF_CLIF_CFG_INITIATOR CLIF_ANA_AGC_REG
# A0, 0D, 03, 06, 47, 02 RF_CLIF_CFG_TARGET CLIF_ANA_AGC_REG
# A0, 0D, 06, 06, 03, 00, 6D, 00, 20 RF_CLIF_CFG_TARGET CLIF_TRANSCEIVE_CONTROL_REG
# A0, 0D, 06, 06, 42, 00, 02, FF, FF RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 03, 06, 37, 08 RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG
# A0, 0D, 06, 32, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 34, 2D, 24, 47, 0C, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 04, 34, 44, 21, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG
# A0, 0D, 04, 46, 44, 26, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 46, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 06, 44, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 04, 56, 44, 22, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_ANA_RX_REG
# A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
# A0, 0D, 04, 5C, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_ANA_RX_REG
# A0, 0D, 06, 54, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 5A, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 98, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_B CLIF_ANA_TX_AMPLITUDE_REG
# A0, 0D, 06, 6C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_ANA_RX_REG
# A0, 0D, 06, 7C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_ANA_RX_REG
# A0, 0D, 06, 8E, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXF CLIF_ANA_RX_REG
# A0, 0D, 06, 94, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXF CLIF_ANA_RX_REG
# A0, 0D, 06, 24, 42, 00, 02, FF, FF RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_AMPLITUDE_REG
# *** ALMSL FW VERSION = 10.05.02 ***
NXP_RF_CONF_BLK_1={
20, 02, C5, 18,
A0, 0D, 03, 00, 40, 03,
A0, 0D, 03, 04, 47, 02,
A0, 0D, 03, 06, 47, 02,
A0, 0D, 06, 06, 03, 00, 6E, 00, 20,
A0, 0D, 06, 06, 42, 00, 00, F8, F8,
A0, 0D, 03, 06, 37, 08,
A0, 0D, 06, 32, 42, F8, 10, FF, FF,
A0, 0D, 06, 34, 2D, 24, 47, 0C, 00,
A0, 0D, 04, 34, 44, 21, 00,
A0, 0D, 04, 46, 44, 26, 00,
A0, 0D, 06, 46, 2D, 15, 25, 0D, 00,
A0, 0D, 06, 44, 42, 88, 10, FF, FF,
A0, 0D, 06, 56, 2D, 05, 5E, 0C, 00,
A0, 0D, 04, 56, 44, 21, 00,
A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00,
A0, 0D, 04, 5C, 44, 26, 00,
A0, 0D, 06, 54, 42, 88, 10, FF, FF,
A0, 0D, 06, 5A, 42, 90, 10, FF, FF,
A0, 0D, 06, 98, 42, 00, 00, F8, F8,
A0, 0D, 06, 6C, 44, A3, 90, 03, 00,
A0, 0D, 06, 7C, 44, A3, 90, 03, 00,
A0, 0D, 06, 8E, 44, 12, 90, 03, 00,
A0, 0D, 06, 94, 44, 12, 90, 03, 00,
A0, 0D, 06, 24, 42, 00, 00, F8, F8
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
NXP_RF_CONF_BLK_2={
20, 02, 71, 03,
A0, 1D, 11, 53, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00,
A0, 1E, 11, 1B, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00,
A0, 92, 45, 23, 04, 50, 10, 00, 9B, 00, 14, 00, FF, 00, 00, 00, 4C, 81, 00, 00, FF, 83, 03, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
NXP_RF_CONF_BLK_3={
20, 02, 2E, 05,
A0, 0D, 06, 00, 35, 50, 00, FF, 02,
A0, 0D, 06, 04, 35, F4, 01, F4, 01,
A0, 0D, 06, 06, 35, FF, 03, FF, 03,
A0, 0D, 06, 07, 35, FF, 01, FF, 02,
A0, 0D, 06, 10, 35, FF, 01, FF, 02
}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
#NXP_RF_CONF_BLK_4={
#}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
#NXP_RF_CONF_BLK_5={
#}
###############################################################################
# NXP RF configuration ALM/PLM settings
# This section needs to be updated with the correct values based on the platform
#NXP_RF_CONF_BLK_6={
#}
###############################################################################
## Set configuration optimization decision setting
## Enable = 0x01
## Disable = 0x00
NXP_SET_CONFIG_ALWAYS=0x00
###############################################################################
# Core configuration extensions
# It includes
# Wired mode settings A0ED, A0EE
# Tag Detector A040, A041, A043
# Low Power mode A007
# Clock settings A002, A003
# PbF settings A008
NXP_CORE_CONF_EXTN={20, 02, 29, 0A,
A0, 06, 01, 01,
A0, 07, 01, 02,
A0, EC, 01, 00,
A0, ED, 01, 00,
A0, 5E, 01, 01,
A0, 40, 01, 01,
A0, DD, 01, 2D,
A0, 96, 01, 01,
A0, 41, 01, 02,
A0, 43, 01, 00
}
###############################################################################
# Core configuration rf field filter settings to enable set to 01 to disable set to 00 last bit
NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 01
}
###############################################################################
# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set to 0x00
NXP_I2C_FRAGMENTATION_ENABLED=0x00
###############################################################################
# Core configuration settings
NXP_CORE_CONF={ 20, 02, 2A, 0E,
28, 01, 00,
21, 01, 00,
30, 01, 08,
31, 01, 03,
32, 01, 60,
38, 01, 01,
33, 00,
54, 01, 06,
50, 01, 02,
5B, 01, 00,
80, 01, 01,
81, 01, 01,
82, 01, 0E,
18, 01, 01
}
###############################################################################
# Mifare Classic Key settings
#NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5,
# A0, 52, 06, D3, F7, D3, F7, D3, F7,
# A0, 53, 06, FF, FF, FF, FF, FF, FF,
# A0, 54, 06, 00, 00, 00, 00, 00, 00}
###############################################################################
# Default SE Options
# No secure element 0x00
# eSE 0x01
# UICC 0x02
NXP_DEFAULT_SE=0x00
###############################################################################
#Enable SWP full power mode when phone is power off
NXP_SWP_FULL_PWR_ON=0x00
###############################################################################
#### Select the CHIP ####
#PN547C2 0x01
#PN65T 0x02
#PN548AD 0x03
#PN66T 0x04
#PN551 0x05
#PN67T 0x06
NXP_NFC_CHIP=0x05
###############################################################################
# CE when Screen state is locked
# Disable 0x00
# Enable 0x01
NXP_CE_ROUTE_STRICT_DISABLE=0x01
#Timeout in secs to get NFCEE Discover notification
NXP_DEFAULT_NFCEE_DISC_TIMEOUT=20
NXP_DEFAULT_NFCEE_TIMEOUT=0x06
#Timeout in secs
NXP_SWP_RD_START_TIMEOUT=0x0A
#Timeout in secs
NXP_SWP_RD_TAG_OP_TIMEOUT=0x01
###############################################################################
#Set the default AID route Location :
#This settings will be used when application does not set this parameter
# host 0x00
# eSE 0x01
# UICC 0x02
DEFAULT_AID_ROUTE=0x00
###############################################################################
#Set the Mifare Desfire route Location :
#This settings will be used when application does not set this parameter
# host 0x00
# eSE 0x01
# UICC 0x02
DEFAULT_DESFIRE_ROUTE=0x00
###############################################################################
#Set the Mifare CLT route Location :
#This settings will be used when application does not set this parameter
# host 0x00
# eSE 0x01
# UICC 0x02
DEFAULT_MIFARE_CLT_ROUTE=0x00
###############################################################################
#Set the default AID Power state :
#This settings will be used when application does not set this parameter
# bit pos 0 = Switch On
# bit pos 1 = Switch Off
# bit pos 2 = Battery Off
# bit pos 3 = Screen Lock
# bit pos 4 = Screen Off
DEFAULT_AID_PWR_STATE=0x19
###############################################################################
#Set the Mifare Desfire Power state :
#This settings will be used when application does not set this parameter
# bit pos 0 = Switch On
# bit pos 1 = Switch Off
# bit pos 2 = Battery Off
# bit pos 3 = Screen Lock
# bit pos 4 = Screen Off
DEFAULT_DESFIRE_PWR_STATE=0x1B
###############################################################################
#Set the Mifare CLT Power state :
#This settings will be used when application does not set this parameter
# bit pos 0 = Switch On
# bit pos 1 = Switch Off
# bit pos 2 = Battery Off
# bit pos 3 = Screen Lock
# bit pos 4 = Screen Off
DEFAULT_MIFARE_CLT_PWR_STATE=0x1B
###############################################################################
# AID Matching platform options
# AID_MATCHING_L 0x01
# AID_MATCHING_K 0x02
AID_MATCHING_PLATFORM=0x01
###############################################################################
#CHINA_TIANJIN_RF_SETTING
#Enable 0x01
#Disable 0x00
NXP_CHINA_TIANJIN_RF_ENABLED=0x01
###############################################################################
#SWP_SWITCH_TIMEOUT_SETTING
# Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60].
# Timeout in milliseconds, for example
# No Timeout 0x00
# 10 millisecond timeout 0x0A
NXP_SWP_SWITCH_TIMEOUT=0x0A
###############################################################################
#Dynamic RSSI feature enable
# Disable 0x00
# Enable 0x01
NXP_AGC_DEBUG_ENABLE=0x00
###############################################################################
#Config to allow adding aids
#NFC on/off is required after this config
#1 = enabling adding aid to NFCC routing table.
#0 = disabling adding aid to NFCC routing table.
NXP_ENABLE_ADD_AID=0x01
###############################################################################
# Enable/Disable checking default proto SE Id
# Disable 0x00
# Enable 0x01
NXP_CHECK_DEFAULT_PROTO_SE_ID=0x01