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7. pmc.txt

* Power Management Controller

Properties:
- compatible: "fsl,<chip>-pmc".

  "fsl,mpc8349-pmc" should be listed for any chip whose PMC is
  compatible.  "fsl,mpc8313-pmc" should also be listed for any chip
  whose PMC is compatible, and implies deep-sleep capability.

  "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
  compatible.  "fsl,mpc8536-pmc" should also be listed for any chip
  whose PMC is compatible, and implies deep-sleep capability.

  "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
  compatible; all statements below that apply to "fsl,mpc8548-pmc" also
  apply to "fsl,mpc8641d-pmc".

  Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
  bit assignments are indicated via the sleep specifier in each device's
  sleep property.

- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
  is the PMC block, and the second resource is the Clock Configuration
  block.

  For devices compatible with "fsl,mpc8548-pmc", the first resource
  is a 32-byte block beginning with DEVDISR.

- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first
  resource is the PMC block interrupt.

- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices,
  this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
  a wakeup source from deep sleep.

Sleep specifiers:

  fsl,mpc8349-pmc: Sleep specifiers consist of one cell.  For each bit
  that is set in the cell, the corresponding bit in SCCR will be saved
  and cleared on suspend, and restored on resume.  This sleep controller
  supports disabling and resuming devices at any time.

  fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
  which will be ORed into PMCDR upon suspend, and cleared from PMCDR
  upon resume.  The first two cells are as described for fsl,mpc8578-pmc.
  This sleep controller only supports disabling devices during system
  sleep, or permanently.

  fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
  first of which will be ORed into DEVDISR (and the second into
  DEVDISR2, if present -- this cell should be zero or absent if the
  hardware does not have DEVDISR2) upon a request for permanent device
  disabling.  This sleep controller does not support configuring devices
  to disable during system sleep (unless supported by another compatible
  match), or dynamically.

Example:

	power@b00 {
		compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
		reg = <0xb00 0x100 0xa00 0x100>;
		interrupts = <80 8>;
	};