mrf24j40.c - Android社区 - https://www.androidos.net.cn/

Kernel | 3.10

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/*
 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
 *
 * Copyright (C) 2012 Alan Ott <alan@signal11.us>
 *                    Signal 11 Software
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/spi/spi.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <net/wpan-phy.h>
#include <net/mac802154.h>
#include <net/ieee802154.h>

/* MRF24J40 Short Address Registers */
#define REG_RXMCR    0x00  /* Receive MAC control */
#define REG_PANIDL   0x01  /* PAN ID (low) */
#define REG_PANIDH   0x02  /* PAN ID (high) */
#define REG_SADRL    0x03  /* Short address (low) */
#define REG_SADRH    0x04  /* Short address (high) */
#define REG_EADR0    0x05  /* Long address (low) (high is EADR7) */
#define REG_TXMCR    0x11  /* Transmit MAC control */
#define REG_PACON0   0x16  /* Power Amplifier Control */
#define REG_PACON1   0x17  /* Power Amplifier Control */
#define REG_PACON2   0x18  /* Power Amplifier Control */
#define REG_TXNCON   0x1B  /* Transmit Normal FIFO Control */
#define REG_TXSTAT   0x24  /* TX MAC Status Register */
#define REG_SOFTRST  0x2A  /* Soft Reset */
#define REG_TXSTBL   0x2E  /* TX Stabilization */
#define REG_INTSTAT  0x31  /* Interrupt Status */
#define REG_INTCON   0x32  /* Interrupt Control */
#define REG_RFCTL    0x36  /* RF Control Mode Register */
#define REG_BBREG1   0x39  /* Baseband Registers */
#define REG_BBREG2   0x3A  /* */
#define REG_BBREG6   0x3E  /* */
#define REG_CCAEDTH  0x3F  /* Energy Detection Threshold */

/* MRF24J40 Long Address Registers */
#define REG_RFCON0     0x200  /* RF Control Registers */
#define REG_RFCON1     0x201
#define REG_RFCON2     0x202
#define REG_RFCON3     0x203
#define REG_RFCON5     0x205
#define REG_RFCON6     0x206
#define REG_RFCON7     0x207
#define REG_RFCON8     0x208
#define REG_RSSI       0x210
#define REG_SLPCON0    0x211  /* Sleep Clock Control Registers */
#define REG_SLPCON1    0x220
#define REG_WAKETIMEL  0x222  /* Wake-up Time Match Value Low */
#define REG_WAKETIMEH  0x223  /* Wake-up Time Match Value High */
#define REG_RX_FIFO    0x300  /* Receive FIFO */

/* Device configuration: Only channels 11-26 on page 0 are supported. */
#define MRF24J40_CHAN_MIN 11
#define MRF24J40_CHAN_MAX 26
#define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
		      - ((u32)1 << MRF24J40_CHAN_MIN))

#define TX_FIFO_SIZE 128 /* From datasheet */
#define RX_FIFO_SIZE 144 /* From datasheet */
#define SET_CHANNEL_DELAY_US 192 /* From datasheet */

/* Device Private Data */
struct mrf24j40 {
	struct spi_device *spi;
	struct ieee802154_dev *dev;

struct mutex buffer_mutex; /* only used to protect buf */
	struct completion tx_complete;
	struct work_struct irqwork;
	u8 *buf; /* 3 bytes. Used for SPI single-register transfers. */
};

/* Read/Write SPI Commands for Short and Long Address registers. */
#define MRF24J40_READSHORT(reg) ((reg) << 1)
#define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
#define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
#define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)

/* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
#define MAX_SPI_SPEED_HZ 10000000

#define printdev(X) (&X->spi->dev)

static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value)
{
	int ret;
	struct spi_message msg;
	struct spi_transfer xfer = {
		.len = 2,
		.tx_buf = devrec->buf,
		.rx_buf = devrec->buf,
	};

spi_message_init(&msg);
	spi_message_add_tail(&xfer, &msg);

mutex_lock(&devrec->buffer_mutex);
	devrec->buf[0] = MRF24J40_WRITESHORT(reg);
	devrec->buf[1] = value;

ret = spi_sync(devrec->spi, &msg);
	if (ret)
		dev_err(printdev(devrec),
			"SPI write Failed for short register 0x%hhx\n", reg);