/* * Misc utility routines for accessing the SOC Interconnects * of Broadcom HNBU chips. * * Copyright (C) 1999-2012, Broadcom Corporation * * Unless you and Broadcom execute a separate written software license * agreement governing use of this software, this software is licensed to you * under the terms of the GNU General Public License version 2 (the "GPL"), * available at http://www.broadcom.com/licenses/GPLv2.php, with the * following added to such license: * * As a special exception, the copyright holders of this software give you * permission to link this software with independent modules, and to copy and * distribute the resulting executable under terms of your choice, provided that * you also meet, for each linked independent module, the terms and conditions of * the license of that module. An independent module is a module which is not * derived from this software. The special exception does not apply to any * modifications of the software. * * Notwithstanding the above, under no circumstances may you combine this * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * * $Id: siutils.h 309193 2012-01-19 00:03:57Z $ */ #ifndef _siutils_h_ #define _siutils_h_ struct si_pub { uint socitype; uint bustype; uint buscoretype; uint buscorerev; uint buscoreidx; int ccrev; uint32 cccaps; uint32 cccaps_ext; int pmurev; uint32 pmucaps; uint boardtype; uint boardrev; uint boardvendor; uint boardflags; uint boardflags2; uint chip; uint chiprev; uint chippkg; uint32 chipst; bool issim; uint socirev; bool pci_pr32414; }; typedef const struct si_pub si_t; #define SI_OSH NULL #define BADIDX (SI_MAXCORES + 1) #define XTAL 0x1 #define PLL 0x2 #define CLK_FAST 0 #define CLK_DYNAMIC 2 #define GPIO_DRV_PRIORITY 0 #define GPIO_APP_PRIORITY 1 #define GPIO_HI_PRIORITY 2 #define GPIO_PULLUP 0 #define GPIO_PULLDN 1 #define GPIO_REGEVT 0 #define GPIO_REGEVT_INTMSK 1 #define GPIO_REGEVT_INTPOL 2 #define SI_DEVPATH_BUFSZ 16 #define SI_DOATTACH 1 #define SI_PCIDOWN 2 #define SI_PCIUP 3 #define ISSIM_ENAB(sih) 0 #if defined(BCMPMUCTL) #define PMUCTL_ENAB(sih) (BCMPMUCTL) #else #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU) #endif #if defined(BCMPMUCTL) && BCMPMUCTL #define CCCTL_ENAB(sih) (0) #define CCPLL_ENAB(sih) (0) #else #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL) #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK) #endif typedef void (*gpio_handler_t)(uint32 stat, void *arg); #define CC_BTCOEX_EN_MASK 0x01 #define GPIO_CTRL_EPA_EN_MASK 0x40 #define GPIO_CTRL_5_6_EN_MASK 0x60 #define GPIO_CTRL_7_6_EN_MASK 0xC0 #define GPIO_OUT_7_EN_MASK 0x80 extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, uint *varsz); extern si_t *si_kattach(osl_t *osh); extern void si_detach(si_t *sih); extern bool si_pci_war16165(si_t *sih); extern uint si_corelist(si_t *sih, uint coreid[]); extern uint si_coreid(si_t *sih); extern uint si_flag(si_t *sih); extern uint si_intflag(si_t *sih); extern uint si_coreidx(si_t *sih); extern uint si_coreunit(si_t *sih); extern uint si_corevendor(si_t *sih); extern uint si_corerev(si_t *sih); extern void *si_osh(si_t *sih); extern void si_setosh(si_t *sih, osl_t *osh); extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); extern void *si_coreregs(si_t *sih); extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val); extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val); extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val); extern bool si_iscoreup(si_t *sih); extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit); extern void *si_setcoreidx(si_t *sih, uint coreidx); extern void *si_setcore(si_t *sih, uint coreid, uint coreunit); extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val); extern void si_restore_core(si_t *sih, uint coreid, uint intr_val); extern int si_numaddrspaces(si_t *sih); extern uint32 si_addrspace(si_t *sih, uint asidx); extern uint32 si_addrspacesize(si_t *sih, uint asidx); extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size); extern int si_corebist(si_t *sih); extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits); extern void si_core_disable(si_t *sih, uint32 bits); extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m); extern bool si_read_pmu_autopll(si_t *sih); extern uint32 si_clock(si_t *sih); extern uint32 si_alp_clock(si_t *sih); extern uint32 si_ilp_clock(si_t *sih); extern void si_pci_setup(si_t *sih, uint coremask); extern void si_pcmcia_init(si_t *sih); extern void si_setint(si_t *sih, int siflag); extern bool si_backplane64(si_t *sih); extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg); extern void si_deregister_intr_callback(si_t *sih); extern void si_clkctl_init(si_t *sih); extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih); extern bool si_clkctl_cc(si_t *sih, uint mode); extern int si_clkctl_xtal(si_t *sih, uint what, bool on); extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val); extern void si_btcgpiowar(si_t *sih); extern bool si_deviceremoved(si_t *sih); extern uint32 si_socram_size(si_t *sih); extern uint32 si_socdevram_size(si_t *sih); extern uint32 si_socram_srmem_size(si_t *sih); extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect, uint8 *remap); extern bool si_socdevram_pkg(si_t *sih); extern bool si_socdevram_remap_isenb(si_t *sih); extern uint32 si_socdevram_remap_size(si_t *sih); extern void si_watchdog(si_t *sih, uint ticks); extern void si_watchdog_ms(si_t *sih, uint32 ms); extern void *si_gpiosetcore(si_t *sih); extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority); extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority); extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority); extern uint32 si_gpioin(si_t *sih); extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority); extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority); extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val); extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority); extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority); extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val); extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val); extern uint32 si_gpio_int_enable(si_t *sih, bool enable); extern void *si_gpio_handler_register(si_t *sih, uint32 e, bool lev, gpio_handler_t cb, void *arg); extern void si_gpio_handler_unregister(si_t *sih, void* gpioh); extern void si_gpio_handler_process(si_t *sih); extern bool si_pci_pmecap(si_t *sih); struct osl_info; extern bool si_pci_fastpmecap(struct osl_info *osh); extern bool si_pci_pmestat(si_t *sih); extern void si_pci_pmeclr(si_t *sih); extern void si_pci_pmeen(si_t *sih); extern void si_pci_pmestatclr(si_t *sih); extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset); extern void si_sdio_init(si_t *sih); extern uint16 si_d11_devid(si_t *sih); extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice, uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader); #define si_eci(sih) 0 static INLINE void * si_eci_init(si_t *sih) {return NULL;} #define si_eci_notify_bt(sih, type, val) (0) #define si_seci(sih) 0 #define si_seci_upd(sih, a) do {} while (0) static INLINE void * si_seci_init(si_t *sih, uint8 use_seci) {return NULL;} #define si_seci_down(sih) do {} while (0) extern bool si_is_otp_disabled(si_t *sih); extern bool si_is_otp_powered(si_t *sih); extern void si_otp_power(si_t *sih, bool on); extern bool si_is_sprom_available(si_t *sih); extern bool si_is_sprom_enabled(si_t *sih); extern void si_sprom_enable(si_t *sih, bool enable); extern int si_cis_source(si_t *sih); #define CIS_DEFAULT 0 #define CIS_SROM 1 #define CIS_OTP 2 #define DEFAULT_FAB 0x0 #define CSM_FAB7 0x1 #define TSMC_FAB12 0x2 #define SMIC_FAB4 0x3 extern int si_otp_fabid(si_t *sih, uint16 *fabid, bool rw); extern uint16 si_fabid(si_t *sih); extern int si_devpath(si_t *sih, char *path, int size); extern char *si_getdevpathvar(si_t *sih, const char *name); extern int si_getdevpathintvar(si_t *sih, const char *name); extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len, const char *name); extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val); extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val); extern void si_war42780_clkreq(si_t *sih, bool clkreq); extern void si_pci_down(si_t *sih); extern void si_pci_up(si_t *sih); extern void si_pci_sleep(si_t *sih); extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm); extern void si_pcie_power_save_enable(si_t *sih, bool enable); extern void si_pcie_extendL1timer(si_t *sih, bool extend); extern int si_pci_fixcfg(si_t *sih); extern void si_chippkg_set(si_t *sih, uint); extern void si_chipcontrl_btshd0_4331(si_t *sih, bool on); extern void si_chipcontrl_restore(si_t *sih, uint32 val); extern uint32 si_chipcontrl_read(si_t *sih); extern void si_chipcontrl_epa4331(si_t *sih, bool on); extern void si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl); extern void si_chipcontrl_srom4360(si_t *sih, bool on); extern void si_epa_4313war(si_t *sih); extern void si_btc_enable_chipcontrol(si_t *sih); extern void si_btcombo_p250_4313_war(si_t *sih); extern void si_btcombo_43228_war(si_t *sih); extern void si_clk_pmu_htavail_set(si_t *sih, bool set_clear); extern uint si_pll_reset(si_t *sih); extern bool si_taclear(si_t *sih, bool details); extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type); extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val); extern void si_pcie_set_request_size(si_t *sih, uint16 size); extern uint16 si_pcie_get_request_size(si_t *sih); extern uint16 si_pcie_get_ssid(si_t *sih); extern uint32 si_pcie_get_bar0(si_t *sih); extern int si_pcie_configspace_cache(si_t *sih); extern int si_pcie_configspace_restore(si_t *sih); extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size); char *si_getnvramflvar(si_t *sih, const char *name); #endif