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4. bindings
5. spmi
6. qcom,spmi-pmic-arb.txt

Qualcomm SPMI Controller (PMIC Arbiter)

The SPMI PMIC Arbiter is found on Snapdragon chipsets.  It is an SPMI
controller with wrapping arbitration logic to allow for multiple on-chip
devices to control a single SPMI master.

The PMIC Arbiter can also act as an interrupt controller, providing interrupts
to slave devices.

See spmi.txt for the generic SPMI controller binding requirements for child
nodes.

See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
generic interrupt controller binding documentation.

Required properties:
- compatible : should be "qcom,spmi-pmic-arb".
- reg-names  : must contain:
     "core" - core registers
     "intr" - interrupt controller registers
     "cnfg" - configuration registers
   Registers used only for V2 PMIC Arbiter:
     "chnls"  - tx-channel per virtual slave registers.
     "obsrvr" - rx-channel (called observer) per virtual slave registers.

- reg : address + size pairs describing the PMIC arb register sets; order must
        correspond with the order of entries in reg-names
- #address-cells : must be set to 2
- #size-cells : must be set to 0
- qcom,ee : indicates the active Execution Environment identifier (0-5)
- qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5)
- interrupts : interrupt list for the PMIC Arb controller, must contain a
               single interrupt entry for the peripheral interrupt
- interrupt-names : corresponding interrupt names for the interrupts
                    listed in the 'interrupts' property, must contain:
     "periph_irq" - summary interrupt for PMIC peripherals
- interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller
- #interrupt-cells :  must be set to 4. Interrupts are specified as a 4-tuple:
    cell 1: slave ID for the requested interrupt (0-15)
    cell 2: peripheral ID for requested interrupt (0-255)
    cell 3: the requested peripheral interrupt (0-7)
    cell 4: interrupt flags indicating level-sense information, as defined in
            dt-bindings/interrupt-controller/irq.h

Example:

	spmi {
		compatible = "qcom,spmi-pmic-arb";
		reg-names = "core", "intr", "cnfg";
		reg = <0xfc4cf000 0x1000>,
		      <0xfc4cb000 0x1000>,
		      <0xfc4ca000 0x1000>;

		interrupt-names = "periph_irq";
		interrupts = <0 190 0>;

		qcom,ee = <0>;
		qcom,channel = <0>;

		#address-cells = <2>;
		#size-cells = <0>;

		interrupt-controller;
		#interrupt-cells = <4>;
	};